This application claims priority to Korean Patent Application No. 2002-61042, filed Oct. 7, 2002 in the Korean Intellectual Property Office, which is incorporated herein by reference.
The present invention relates to circuits and methods for providing page mode operation in a semiconductor memory device having a partial activation architecture.
There is a continual demand for semiconductor devices such as DRAM (dynamic random access memory) devices, which provide fast and efficient memory access operations (read and write operations). But as the memory access speed of a DRAM increases, the power dissipation generally increases, which can pose serious problems. Therefore, when developing a semiconductor memory device, the operating speed and power dissipation is a trade-off relationship that is typically considered. Some techniques for controlling power dissipation while providing high-speed operation have focused on reducing the memory cell array currents. By way of example, semiconductor memory devices having a partial activation architecture have been developed, which enables one of a plurality of memory cell array blocks to be activated for performing a memory access operation in an activated memory block. One example of a semiconductor device having a partial activation structure is a FCRAM (fast cycle random access memory), which was developed by Fujitsu Ltd.
FIGS. 1A through 1C illustrate a hierarchical memory architecture of a semiconductor memory device according to the prior art, which enables partial activation of blocks of memory cells. As shown in FIG. 1A, a semiconductor memory device (10) includes a plurality of memory banks (10A, 10B, 10C, 10D). Each memory bank represents, for example, a logical unit of memory in a PC, and each bank may consist of one or more memory modules (e.g., DIMM (Dual In-line Memory Module), SIMM (Single In-Line Memory Module)). Each memory bank (10A, 10B, 10C, 10D) is further logically divided into a plurality of memory cell array blocks. For instance, as depicted in the exemplary embodiment of FIG. 1B, the memory bank (10A) comprises four memory cell array blocks (100a, 100b, 100c, 100d).
In addition, each memory cell array block (100a, 100b, 100c, 100d) is further logically divided into a plurality of sub-memory cell array blocks (or column blocks), wherein each sub-memory cell array block is controlled by associated control circuitry. For instance, as depicted in the exemplary embodiment of FIG. 1C, the memory cell array block (100a) comprises four sub-memory cell array blocks (101, 102, 103, 104). The memory cell array block (100a) further comprises a plurality of sub-wordline drivers (105, 106, 107, 108), wherein each sub-wordline driver is associated with one of the sub-memory cell array blocks (101, 102, 103, 104).
Each sub-wordline driver (105, 106, 107 and 108) activates a corresponding sub-wordline (WL1, WL2, WL3, WL4) of the corresponding column block. More specifically, wordlines of memory block (100a) are formed over the memory block (100a) using a global wordline framework, and such wordlines are activated by a row decoder based on an input row address (wordline address). The sub-wordlines are formed over corresponding column blocks and the sub-wordline drivers (105, 106, 107, 108) control activation of corresponding sub-wordlines. For example, in the exemplary embodiment of FIG. 1C, when a row address and a column block selection address are input to the memory device, a global wordline corresponding to the input row address is activated by a row decoder. Furthermore, the input column block selection address is used to activate one of the column blocks (101, 102, 103, 104), which causes a corresponding sub-wordline driver (105, 106, 107, 108) to activate a corresponding sub-wordline having the same address as the activated (global) wordline.
The memory framework depicted in FIGS. 1A-C is one example of a memory framework that can be used for providing a partial activation semiconductor memory device, such as an FCRAM, whereby one of the sub-memory cell array blocks (101, 102, 103, 104) can be activated using, for example, a column block address (CBA) to perform data access or refresh operations. For instance, in the exemplary embodiment of FIG. 1C, since the memory cell array block (100a) comprises four sub-memory blocks (101, 102, 103, 104), a two-bit CBA can be used to select one of the four column blocks (sub-memory blocks), although one of ordinary skill in the art readily will appreciate that the memory framework can be designed with more or less column blocks that are individually addressable by predetermined column block selection addresses.
To perform a memory access operation using the memory framework shown in FIGS. 1A-1C, one of the memory banks (10A, 10B, 10C, 10D) is initially selected in response to a predetermined bank address, and then a memory cell array block (100a, 100b, 100c, 100d) within the selected memory bank is selected in response to a predetermined address (e.g., row address or any other address depending on the addressing scheme). Then, a row address (RA) and column block selection address (CBA) are input to activate a global wordline (based on the decoding results of the input row address of the row decoder) and to activate a column block of the selected memory cell array block (based on the input CBA). Then, only the sub-wordline of the selected column block is activated (having the same address as the activated global wordline) by the corresponding sub-wordline driver.
For example, in the exemplary embodiment of FIG. 1C, when a column block selection address 00 is input, a sub-wordline WL1 corresponding to the first column block (101) is activated based on the input row address. When the column block selection address 01 is input, a sub-wordline WL2 corresponding to the second column block (102) is activated. When the column block selection address 10 is input, a sub-wordline WL3 corresponding to the third column block (103) is activated. When the column block selection address 11 is input, a sub-wordline WL4 corresponding to the fourth column block (104) is activated. Thus, only one-quarter of the memory cells having the same row address are activated. The data is then input/output to/from the activated column block depending on the input column line address(es). In addition, the sub-wordline of the activated column block is automatically inactivated, i.e., precharged, after a predetermined amount of time.
A FCRAM implements a partial activation mode to reduce current dissipation and to improve access speed. In a FCRAM, the tRAC (active restore time) and tRC (row precharge time) are 22 ns and 25 ns, respectively, which represents improvements for tRAC and tRC by 10% and 50%, respectively, as compared to conventional DRAMs.
There are some problems associated with operating a DRAM device in a partial activation mode as compared to a conventional DRAM. For example, it is difficult to perform a xe2x80x9cpage modexe2x80x9d operation for reading/writing data in a DRAM operating in a partial activation mode. As in known in the art, xe2x80x9cpage modexe2x80x9d generally denotes an operation mode in which data is input/output to/from a plurality of memory cells having the same row address X by changing only a column address Y, after the row address X is input once. Conventional DRAM devices operate in a xe2x80x9cpage modexe2x80x9d to provide increased memory access speed, while providing a reduction in the power consumption.
A page mode operation is difficult to implement in a DRAM that operates in a partial activation mode, because, as discussed above with reference to FIG. 1C, the memory cells connected to the same row address (global wordline address) are selectively activated/controlled based on the column block selection address, which is input with the row address. More specifically, when a DRAM having an n-bit column block selection address is operated in a partial activation mode, it is necessary to input the same row address a maximum number of 2n times in order to input/output data to/from memory cells in all column blocks for the same row address. Indeed, with conventional designs, when a given row address is input with an active command signal ACT, the next address (and active command ACT) may only be input after a predetermined time, i.e., tRC, in the case of the FCRAM, because a row precharge operation is automatically performed after a predetermined time from the input of a row address. Therefore, with a FCRAM having an n-bit column block selection address, in order to input/output a data to/from memory cells having the same row address in all the column blocks, the memory access time is equal to a maximum time of tRCxc3x972n plus the data input/output time. These concepts will now be explained by way of example with reference to FIGS. 1C and 2.
FIG. 2 is an exemplary timing diagram illustrating a memory access operation of a conventional semiconductor memory device having a partial activation framework as described above. More specifically, the example of FIG. 2 illustrates a read operation of a conventional semiconductor device having the partial activation structure as shown in FIG. 1C, wherein the read operation is performed using a burst mode where the burst length is 4. In the example of FIG. 2, each input row address X is assumed to be the same. Referring to FIG. 2, a first active command ACT and a row address X and column block selection address CB1 are input synchronously with a clock CLK signal at clock cycle C1. In response, the first column block (101) is selected by the column block selection address CB1 and the word line WL1 corresponding to the input row address X is activated in the first column block (101). When a reading command/RD and a column address Y are input at a subsequent clock cycle C2, one column corresponding to the column address Y is selected so that data is output from the memory cell located at the intersection of the activated word line WL1 and the selected column line. Since the burst length is 4, four data bits DQ are successively output according to one reading command/RD starting from the input column address, for example.
In the conventional design, a row precharge is automatically started after about three (3) cycles from the clock cycle C1 when the active command ACT is applied (i.e., row precharge starts at clock cycle C4). The activated sub-wordline WL1 is then inactivated in response to the commencement of the row precharge operation. A subsequent active command ACT and row address X and a column block selection address CB2 are input at a clock cycle C6 after the row precharge operation is ended. Since the row precharge is automatically started after a predetermined amount of time from the input of an active command ACT, a subsequent active command ACT can be applied only when the row precharge operation is ended. Here, the period of time from the input of an active command ACT to the input of a subsequent active command ACT is referred to as the tRC (row precharge time). In response to the row address X and the column block selection address CB2 input at the clock cycle C6, a corresponding word line WL2 in the second column block (102) is activated. Then, a row precharge is automatically started at clock cycle C9, which is three (3) clock cycles from the input of the active command ACT at clock cycle C6. Therefore, the subsequent active command ACT, row address X, and column block selection address CB3 can only be applied at clock cycle C11 when the precharge operation of the activated sub-wordline WL2 is ended. Accordingly, as described above, in a conventional DRAM device (such as a FCRAM) that automatically performs a precharge operation after a predetermined time from the input of a command, a subsequent row address can only be input after an amount of time tRC, even when the subsequent row address is the same as the previously input row address.
Therefore, although a conventional DRAM device (such as an FCRAM), in which an n-bit column block selection address allows selection of one of 2n column blocks of memory in a partial activation mode of operation, can provide an improvement in the I/O speed of memory accesses when different row addresses are input, because the partial activation mode requires a precharge operation to be performed after a predetermined time from the input of the given row address (i.e., the input of an active command), when the same row address is input, the device may provide an I/O memory access speed that is slower than that of other conventional semiconductor memory devices (e.g., SDRAM, DDR DRAM).
Accordingly, it is desirable to provide circuits and methods that would provide an increase the I/O speed of memory accesses in a DRAM having a partial activation framework when memory accesses are performed for a previous and subsequent row address that are the same.
The present invention is directed to a semiconductor memory device having a partial activation framework, which provides an efficient page mode operation while operating in a partial activation mode. The present invention is further directed to control circuits and methods that enable a page mode operation (for read and write data accesses) in a semiconductor memory device (such as a DRAM, FCRAM) having a partial activation framework, resulting in an improved data access speed when data is written/read from memory locations having the same wordline address.
In one embodiment, a method for accessing data in a memory device comprises activating a first wordline corresponding to a first address to perform a data access operation, receiving a second address after the first address, if the second address is the same as the first address, generating a page mode enable signal for maintaining an activated state of the first wordline corresponding to the first address while activating a second wordline corresponding to the second address, and deactivating the first and second wordlines in response to disabling of the page mode enable signal.
In another embodiment, a semiconductor memory device comprises a memory cell array comprising a plurality of memory blocks, a command decoder for decoding command signals and outputting decoded command signals to perform a data access operation, an address comparator for comparing a first address corresponding to an activated first wordline to a second address received after the first address, and generating a page mode enable signal if the first address and the second address are the same, and a precharge control circuit for controlling a precharge operation, wherein the precharge control circuit is responsive to the page mode enable signal to prevent a precharge operation of the activated first wordline while a second wordline corresponding to the second address is activated to perform a data access operation.
Preferably, the memory cell array comprises a partial activation framework, wherein each memory block is individually addressable by a block address. A data access operation comprises a page mode operation where data is accessed for one or more memory cells having the same row address in a same memory block or in a different memory block. Data can be accessed using a burst mode of operation.
In yet another embodiment, the address comparator comprises means for storing the first address, means for comparing the second address to the first address to determine if the first and second address are the same, and means for outputting the page mode enable signal from the comparator if the first and second address are the same.
In another embodiment, the semiconductor memory device comprises a command shifter circuit, operatively connected to an output of the command decoder and address comparator, wherein in response to the page mode enable signal output from the address comparator, the command shifter delays a write command signal output from the command decoder by a predetermined first delay time. In one embodiment, the command shifter circuit comprises a clock shifter for delaying the write command signal, the clock shifter comprising a plurality of serially connected inverters. In another embodiment, the command shifter circuit comprises a clock shifter for delaying the write command signal, the clock shifter comprising a plurality of serially connected flip-flops.
In yet another embodiment, in response to the write command signal, the precharge control circuit delays the page mode enable signal by a predetermined second delay time to generate a delayed page mode enable signal. The delayed page mode enable signal prevents a precharge operation of activated wordlines.
These and other embodiments, aspects, features and advantages of the present invention will be described and become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.